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Combinational Logic Design

About combinational logic circuits

  • combinational circuits / sequential circuit

  • combinational gate:

  • a node can only be the output of one element (except 3-stage gate, can use control signal to avoid)
  • loop is not allowed (it will lead memory function)
  • design choice:
  • 2-level & multi-level
    • gate delay
    • fan-in / fan-out
    • trade-off between cost and speed

  • functional blocks

  • procedure :

  • Specification :
    • use text, HDL... to write specification
  • formulation :
    • derive a truth table or initial boolean equations to define the required relationships between the inputs and outputs (逻辑赋值)
  • optimization :
    • 2-level or mulitple-level
  • technology mapping :
    • map the logic diagram to netlist to the implementation technology selected.
  • verification

Note

  • 行为描述：描述一个逻辑功能 门级描述：利用利用门级符号描述
  • AOI : 与或非门

Some classic/basic designs

  • multiple-bit rudimentary functions : a wide line is used to represent a bus which is a vector signal

  • decoding : the conversion of an n-bit input code to an m-bit output with \(n \leq m \leq 2^n\) such that each valid code word produces a unique output, each output represent a minterm (n-to-m line decoders).

Note

  • 地址译码器，显式译码器……
  • 多输入的译码器可以拆成多个输入较小的译码器

Example

\(\text{7-128 decoders} = \text{3-8 decoders} + \text{4-16 deciders} + 8 \times 16 \text{ 2-input AND gate}\)

  • demulitiplexer : 带始能的译码器

Note

译码器加或门可以实现任何函数

  • 七段数码管

    • display——common Anode/Common Cathode

  • Encoder :

    • priority encoder: highest priority…

  • Multiplexer : \(n\) control inputs ( \(S\) ), and \(m\) information inputs ( \(I\) )

    • 2-to-1-Line Multiplexer : \(Y = \overline{SI_0}+SI_1\) (decoder + AND-OR)
    • Other selection implementation : Using 3-state logic / transmission gate in place AND-OR / decoder

    Note

    • 数码管数字分别快速循环显示，视觉暂留导致像同时出现
    • 多路选择器也可以实现任何函数，不过开销较大
    • 将某个控制信号放到 \(I\) 可以减小开销
    • one-time programming / FPGA

Timing Analysis

  • Propagation delay : \(T_{pd} = \text{max delay from input to output}\)

  • Contamination delay : \(T_{cd} = \text{min delay from input to output}\)

  • The critical (longest) path : \(T_{pd} \text{ of the circuit} = \sum \text{all } T_{pd} \text{ of circuit elements along the critical path}\)

  • The shortest path : \(T_{cd} \text{ of the circuit} = \sum \text{all } T_{cd} \text{ of circuit elements along the shortest path}\)

  • Race hazard

  • Glitch : when a single input change causes multiple output changes.

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